A low-overhead coherence solution for multiprocessors with private cache memories

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A low-overhead coherence solution for multiprocessors with private cache memories

Full text

Pdf (708 KB)

Source

International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 284 - 290

Year of Publication: 1998

ISBN:1-58113-058-9

Authors

Mark S. Papamarcos	Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield, Urbana, IL
Janak H. Patel	Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield, Urbana, IL

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 35, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTex EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/285930.285987 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Archibald83	J. Archibald and J. L. Baer, "An Economical Solution to the Cache Coherence Solution," Unlverslty of Washington Technical Report 83-10-07, October, 1 983 ~
	Bean79	B. M. Bean, K. Langston, R. Partridge, and K. K. Sy, "Bias Filter Memory for Filtering out Unnecessary Interrogations of Cache Directorles in a Hultiprocessor System, " Unlted States Patent 4,142,234, February 27, 1979.
	Censier78	L. M. Cennler and P. Feautrler, "A New Solutlon to Coherence Problems in Hultlcac~e Systeas, " /EEE Trans. ComuS., vol. C-27, December 1978, pp. 1112-1118.
	Conti69	C. J. Contl, "Concepts for Buffer Storage," IEEE ~. ~ News, vol. 2, March 1969, pp. 9-13.
	Dubois82	M. Dubols and F. A. Brlggs, "Effects of Cache Coherency in Hultlprocessors," IEEE j~. ., vol. C-31, November 1982, pp. 1083- 1099.
	Goodman83	James R. Goodman, Using cache memory to reduce processor-memory traffic, Proceedings of the 10th annual international symposium on Computer architecture, p.124-131, June 13-17, 1983, Stockholm, Sweden
	Kaplan73	K. R. Kaplan and R. O. Winder, "Cache-Based Computer Systems," ~, March 1973, PP. 30-36.
	Meade70	R. H. Meade, "On Memory System Design," ~LF~ Proc. FJCC, vol. 37, 1970, pp. 33-43.
	Norton82	R. L. Norton and J. A. Abraham, "Using Write Back Cache to Improve Performance of Multluaer Hultiprocessors," Prec. 1982 Int. Conf. on ~ 2rocessin~, August 1982,. pp. 326-331.
	Patel82	J. H. Patel, "Analysis of Multlprocessors wlth Private Caohe Memories," IEEE Trans. ~., vol. C-31, April 1982, pp. 296-30~.
	Rao78	Gururaj S. Rao, Performance Analysis of Cache Memories, Journal of the ACM (JACM), v.25 n.3, p.378-395, July 1978 [doi>10.1145/322077.322081]
	Smith82	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
	Strecker76	WILLIAM D. STRECKER, Cache memories for PDP-11 family computers, Proceedings of the 3rd annual symposium on Computer architecture, p.155-158, January 19-21, 1976
	Tang76	C. K. Tang, "Cache System Design in the Tightly Coupled Multiprocessor System," rJ;;~. ~, vol. 45, 1976, pp. 749-753.
	Yeh83	P. C. C. Yeh, J. H. Pate1, and E. S. Davidson, "Shared Cache for Multiple-Stream Curepurer Systems, " IEEE ~.gI~. ~., vol. C- 32, January 1983, pp. 38-47.
	Yen82	W. C. Yen and K. S. Fu, "Coherence Problem in a Multlcache System," Proc. 1982 int. Conf. on ~ Processln~, 1982, pp. 332-339.