A. R. Hurson
220 Pond Lab.
Department of Computer Science and Engineering
The Pennsylvania State University
University Park, PA 16802
Phone: (814) 863-1187
Fax: (814) 8653176
Email: hurson@cse.psu.edu
Biographical Information
A. R. Hurson is a Computer Science and Engineering Faculty at The
Pennsylvania State University. He has published over 160 technical papers
in areas including computer architecture, parallel processing, dataflow
architecture, database systems and database machines, multidatabases,
object oriented databases, and VLSI algorithms. He is the co-author of
the IEEE Tutorials on Parallel Architectures for Database Systems,
Multidatabase systems: An advanced solution for global information
sharing, Parallel architectures for data/knowledge base systems, and
Scheduling and Load Balancing in Parallel and Distributed Systems. He is
also the co-founder of the IEEE Symposium on Parallel and Distributed
Processing.
Professor Hurson has been active in various IEEE/ACM Conferences
and has given tutorials for various conferences on dataflow processing,
database management systems, supercomputer technology,
data/knowledge-based systems, scheduling and load balancing, and parallel
computing. He served as a member of the IEEE Computer Society Press
Editorial Board and an IEEE Distinguished speaker. Currently, he is
serving in the IEEE/ACM Computer Sciences Accreditation Board and as the
editor of IEEE transactions on computers.
Suggested Lecture Topics
Mobile Computing and Global Information Sharing Process
The traditional notion of timely and reliable access to global information
in a distributed or multidatabase system must be expanded. Users are
becoming much more demanding in that they desire and sometimes even
require access to information anytime, anywhere. The extensive diversity
in the range of information that is accessible to a user at any given time
is also growing at a rapid rate. This information can include data from
legacy database systems, database systems, data warehouses, information
services, and the almost limitless information on the Internet and World
Wide Web. Furthermore, rapidly expanding technology is making available a
wide breadth of devices through which access to this enormous amount of
diverse data is possible. For example, the user may access information
from a desktop workstation connected to a LAN, or from a laptop computer
via modem, or from a hand held device via a wireless connection. All of
these devices have different memory, storage, display, and computational
power. This talk investigates various effects of mobile computing on
database issues and proposes a new global information sharing environment.
Finally, several research directions within this new environment is
addressed.
Cache Memories for dataflow systems
The dataflow model of computation, particularly the recent trend in
combining dataflow processing with control-flow processing, provides
attractive alternatives in the design of new computer architectures. This
marriage has also motivated researchers to analyze the applicability of
the familiar concepts within the framework of this new architectural
model. The concept of cache memory has proven its effectiveness in the
traditional control-flow architecture due to the spatial and temporal
localities that govern the organization of the conventional programming
environment. Therefore, it will be interesting to investigate the
presence of localities in dataflow programs and analyze whether the cache
can be incorporated into dataflow architectures. This lecture addresses
the application of cache memory in the dataflow environment. Presence of
localities in dataflow programs is discussed and techniques to exploit
localities in a dataflow programs are analyzed.
Parallelization of Loops
Since loops in programs are the major source of parallelism, considerable
research has been focused on strategies for parallelizing loops. The key
goal is to maximize parallelism while minimizing the processor load
imbalances and network communication. For DOALL loops, loops can be
allocated to processors either statically or dynamically. When the
execution times of individual iterations vary, dynamic schemes can achieve
better load balance, albeit at a higher run-time scheduling cost. The
inter-iteration dependencies of DOACROSS loops can be constant (regular
DOARCOSS loops) or variable (irregular DOACROSS loops). This talk
presents introduces several loop allocation techniques for parallelizing
DOALL, regular, and irregular DOACROSS loops. Furthermore, it analyzes
these techniques for their complexity, scheduling overhead, communication
cost, processor utilization and expected speedup. Finally, it proposes
and analyzes two loop allocation techniques for regular DOACROSS loops,
known as Staggered distribution (SD) and Cyclic Staggered (CSD)
distribution.
Association for Computing Machinery Technology Outreach Program