People of ACM - Hemangee Kapoor

December 6, 2022

What is an interesting challenge your research group at IIT Guwahati is working on right now?

My research group at IIT Guwahati works in the broad area of computer architecture, with a focus on improving the effective utilization of emerging non-volatile memory technologies. Non-volatile memories, on account of their low leakage power and higher density, are a good replacement for power hungry static random-access memory (SRAM) and dynamic random-access memory (DRAM) technology-based devices. However, they are slow in write access times and have limited endurance compared to others.

The data access patterns of the applications are not uniformly distributed and lead to several writes to certain memory locations compared to others. Such heavily written locations are prone to wear-out and, once they become unreliable, it is not possible to use the complete memory device without error corrections.

We handle this non-uniformity using three major approaches: (i) we observe application access patterns to develop methods which evenly distribute the accesses across the overall memory capacity in order to reduce the wear-out pressure on heavily written locations; (ii) we observe the redundancy in data values in order to propose methods that avoid writing such redundant values, thus prolonging the wear-out; and (iii) we redirect frequent writes to temporary SRAM/DRAM partitions, sparing the non-volatile memory (NVM) from getting written with such frequent accesses. This method utilizes the concept of hybrid memories.

Another interesting problem my group works on is in near-memory accelerator design for neural networks. Convolutional neural networks (CNNs) have widespread use in several applications, especially in the domain of visual imagery or computer vision. The CNN models have grown deeper with several hidden layers to achieve high accuracy and learn better features. Consequently, real-time inference has become costly in terms of computations and memory requirements. To handle this computation challenge, we work on the design of accelerators: (i) that are area and power efficient for close integration with memory; and (ii) which also exploit sparsity in the inputs and models to eliminate in-effectual computations, thus saving on energy and execution time.

Will you explain what non-volatile memory is and why its further development is important to the field now?

Current generation multi-core systems need an equally large on-chip memory to satisfy the data demands of the ever-growing applications. This large memory occupies a significant area of the chip real estate and takes a considerable share of the power budget. At the same time, such highly-integrated systems have limits on energy consumption to ensure that the temperature is under the thermal design power (TDP) budget. Conventional SRAM and DRAM memories have power and scalability limitations since their energy leakage is significant. Emerging NVM have high density, good scalability, and low leakage power consumption which makes them an attractive alternative in the memory hierarchy.

NVMs, as the name suggests, are non-volatile—meaning they can retain the data over a prolonged duration even after powering off. Apart from server scale computing, the other target applications for the use of NVMs are devices such as IoT nodes that support workloads including AI tasks. As the edge nodes may turn off computation to save battery power, the memory elements must be non-volatile to retain the data.

Although we see great utility for NVMs, the inherent physics results in slower data writes and weaker cell endurance, i.e., the number of writes a cell can handle before it fails to store values reliably. These issues must be addressed to bring NVM in the main-stream usage. Additionally, NVMs are also prone to data security attacks due to their longer retention of values, so the data needs to be encrypted before storing. Application of encryption algorithms results in changing substantial amount of data leading to an increase in the number of bits that get flipped on every write. These increased bit-flips lead to a further reduction in the lifetime of the NVMs. Therefore, we need effective methods for controlling the bit-flips while writing the encrypted data.

In the long-term, we see a trend towards edge computing leading to skyrocketing generation of data. Data creation is also fueled by 5G networks, social media, image processing and real-time voice processing. In autonomous vehicles, there will be online data processing and storage, making the use of NVMs beneficial. However, the wear-out is a concern, as it is difficult to replace the devices in manufactured vehicles. The longevity of NVM in edge or Internet of Things (IoT) deployments is crucial for their service guarantees, which makes effective lifetime improvement methods a need of the hour.

In one of your most cited papers, “A Security Framework for NoC Using Authenticated Encryption and Session Keys,” which was written in 2013, you and your co-authors presented a security framework for Network-on-Chip (NoC) systems. How have the insights you presented in this paper held up since then? What is an important security challenge in computer architecture right now?

In our paper, we proposed a security framework for NoC-based architectures that divided the System-on-Chip (SoC) into secure and non-secure zones. Subsequently, it employed authenticated encryption to ensure communication among the cores. Specialized session keys were used to establish communication of a non-secure core with a secure core. The proposed scheme focused on how to prevent the critical information stored inside a secure core from unauthorized access.

The on-chip interconnect helps in communication among all the IP cores including memory, input-output devices, and processors. With the increasing demand for multiple cores, it has become imperative to use scalable interconnects. In addition, the usage of third-party IPs has increased over the years including NoC IPs. A compromised NoC IP can be a security threat to the system because the interconnect has access to all the system data. This can lead to attacks like data integrity, denial-of-service, eavesdropping, buffer-overflow, and side-channel attacks to name a few.

NoC IPs are now used in a variety of deployments such as automotive, tablets, mobile phones, etc. In general, such edge deployments have a wider variety of requirements including energy efficiency, domain-specific implementations, and real-time constraints that need to be satisfied in a resource constrained manner. For example, pausing the system to check for malfunction is not an option in an automotive setup as it may lead to catastrophic consequences. We need more innovative and lightweight solutions to support these new specialized application domains. Interested readers can refer to the latest survey of NoC security attacks and countermeasures published in ACM Computing Surveys. An overview of work done in cybersecurity in India is also available in our recent CACM India region special section.

What was a challenge of serving as a co-guest editor of the Communications of the ACM special section on the India Region? What did you learn from this experience?

Serving as a co-guest editor for the CACM special section was my first experience in such a role. I felt privileged and happy to get this opportunity. It was a challenging task, because our team had a big responsibility to accurately represent the advances in computing taking place in the India region. After publishing the call for contributions, we also explored various research groups within the region to identify popular and useful topics that we could bring forth to a wider audience. Attracting articles and reaching out to researchers in neighboring countries was done to cover topics from the entire sub-continent.

Shortlisting the articles was another task which needed meticulousness, because we wanted to offer maximum variety while maintaining the quality of the submissions. We kept a mix of articles that covered products and services, as well as articles that addressed the current need for online education platforms and diversity in education. Although we could not shortlist articles from some aspirational institutions, the feedback provided to the authors will help them to improve their future contributions.

During the process, I learned to communicate with authors, convince them to write within the word limit, and ensure that the research coverage was adequate. For certain topics, to guarantee coverage over the region, we required inputs from various organizations and institutions. The task also required professional assistance for compiling the data. This process gave me the experience of collating information from diverse sources.

I am thankful to my co-guest editors and the CACM editorial staff as well as several experts who helped during the reviews and final selection. The entire process, from the call for submissions up to publishing, has boosted my skill as a team member.

Hemangee K. Kapoor is a Professor and Associate Dean at the Indian Institute of Technology (IIT) Guwahati. Her current research interests include multiprocessor computer architecture, emerging memory technologies, power-aware computing, and accelerators for neural networks.

At ACM, she has been the Vice President of the ACM India Council (2020-2022) and presently serves as a member of the ACM Council for Diversity, Equity and Inclusion (DEI). She was also the co-guest editor for the November 2022 Communications of the ACM special section on the India Region.